1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a semiconductor memory apparatus that allocates different read/write operating time to every bank.
2. Related Art
Generally, in a semiconductor memory apparatus, data is stored in a capacitor of a memory cell. At this time, the semiconductor memory apparatus performs a periodic refresh operation in order to retain the data of the cell. Then, the semiconductor memory apparatus reads or writes the data through bit lines, and precharges the used bit lines with a predetermined voltage.
A general semiconductor memory apparatus sequentially performs a refresh operation, a read/write operation, and a precharge operation. The operating specifications of the semiconductor memory apparatus are described in the standards issued by JEDEC (Joint Electron Device Engineering Council), which is an international standardization organization that deliberates and issues the unified standards for electronic devices, such as integrated circuits (IC)). In compliance with the JEDEC standards, the semiconductor memory apparatus needs to ensure a time required until a precharge operation is completed after a refresh operation (hereinafter, the time is referred to as “tRC”), a time required until a read/write operation is completed (hereinafter, referred to as “tRAS”), and a time required until a precharge operation is completed (hereinafter, referred to as “tRP”) That is, the tRC is a time between an active signal and a precharge signal, and the tRAS and the tRP need to be ensured in the tRC.
However, the semiconductor memory apparatus according to the related art may have the same tRC with respect to each of the active signals that are sequentially input. In this case, the same tRC may cause an error in a bank that has a slow response speed with respect to the read/write operation.